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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">SCTLR_EL2, System Control Register (EL2)</h1><p>The SCTLR_EL2 characteristics are:</p><h2>Purpose</h2>
        <p>Provides top level control of the system, including its memory system, at EL2.</p>

      
        <p>When <span class="xref">FEAT_VHE</span> is implemented, and the value of <a href="AArch64-hcr_el2.html">HCR_EL2</a>.{E2H, TGE} is {1, 1}, these controls apply also to execution at EL0.</p>
      <h2>Configuration</h2><p>AArch64 System register SCTLR_EL2 bits [31:0] are architecturally mapped to AArch32 System register <a href="AArch32-hsctlr.html">HSCTLR[31:0]</a>.</p>
        <p>If EL2 is not implemented, this register is <span class="arm-defined-word">RES0</span> from EL3.</p>

      
        <p>This register has no effect if EL2 is not enabled in the current Security state.</p>
      <h2>Attributes</h2>
        <p>SCTLR_EL2 is a 64-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="1"><a href="#fieldset_0-63_63-1">TIDCP</a></td><td class="lr" colspan="1"><a href="#fieldset_0-62_62-1">SPINTMASK</a></td><td class="lr" colspan="1"><a href="#fieldset_0-61_61-1">NMI</a></td><td class="lr" colspan="1"><a href="#fieldset_0-60_60-1">EnTP2</a></td><td class="lr" colspan="1"><a href="#fieldset_0-59_59-1">TCSO</a></td><td class="lr" colspan="1"><a href="#fieldset_0-58_58-1">TCSO0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-57_57-1">EPAN</a></td><td class="lr" colspan="1"><a href="#fieldset_0-56_56-1">EnALS</a></td><td class="lr" colspan="1"><a href="#fieldset_0-55_55-1">EnAS0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-54_54-1">EnASR</a></td><td class="lr" colspan="1"><a href="#fieldset_0-53_53-1">TME</a></td><td class="lr" colspan="1"><a href="#fieldset_0-52_52-1">TME0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-51_51-1">TMT</a></td><td class="lr" colspan="1"><a href="#fieldset_0-50_50-1">TMT0</a></td><td class="lr" colspan="4"><a href="#fieldset_0-49_46-1">TWEDEL</a></td><td class="lr" colspan="1"><a href="#fieldset_0-45_45-1">TWEDEn</a></td><td class="lr" colspan="1"><a href="#fieldset_0-44_44-1">DSSBS</a></td><td class="lr" colspan="1"><a href="#fieldset_0-43_43-1">ATA</a></td><td class="lr" colspan="1"><a href="#fieldset_0-42_42-1">ATA0</a></td><td class="lr" colspan="2"><a href="#fieldset_0-41_40-1">TCF</a></td><td class="lr" colspan="2"><a href="#fieldset_0-39_38-1">TCF0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-37_37-1">ITFSB</a></td><td class="lr" colspan="1"><a href="#fieldset_0-36_36-1">BT</a></td><td class="lr" colspan="1"><a href="#fieldset_0-35_35-1">BT0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-34_34">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-33_33-1">MSCEn</a></td><td class="lr" colspan="1"><a href="#fieldset_0-32_32-1">CMOW</a></td></tr><tr class="firstrow"><td class="lr" colspan="1"><a href="#fieldset_0-31_31-1">EnIA</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_30-1">EnIB</a></td><td class="lr" colspan="1"><a href="#fieldset_0-29_29-1">LSMAOE</a></td><td class="lr" colspan="1"><a href="#fieldset_0-28_28-1">nTLSMD</a></td><td class="lr" colspan="1"><a href="#fieldset_0-27_27-1">EnDA</a></td><td class="lr" colspan="1"><a href="#fieldset_0-26_26-1">UCI</a></td><td class="lr" colspan="1"><a href="#fieldset_0-25_25">EE</a></td><td class="lr" colspan="1"><a href="#fieldset_0-24_24-1">E0E</a></td><td class="lr" colspan="1"><a href="#fieldset_0-23_23-1">SPAN</a></td><td class="lr" colspan="1"><a href="#fieldset_0-22_22-1">EIS</a></td><td class="lr" colspan="1"><a href="#fieldset_0-21_21-1">IESB</a></td><td class="lr" colspan="1"><a href="#fieldset_0-20_20-1">TSCXT</a></td><td class="lr" colspan="1"><a href="#fieldset_0-19_19">WXN</a></td><td class="lr" colspan="1"><a href="#fieldset_0-18_18-1">nTWE</a></td><td class="lr" colspan="1"><a href="#fieldset_0-17_17">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-16_16-1">nTWI</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_15-1">UCT</a></td><td class="lr" colspan="1"><a href="#fieldset_0-14_14-1">DZE</a></td><td class="lr" colspan="1"><a href="#fieldset_0-13_13-1">EnDB</a></td><td class="lr" colspan="1"><a href="#fieldset_0-12_12">I</a></td><td class="lr" colspan="1"><a href="#fieldset_0-11_11-1">EOS</a></td><td class="lr" colspan="1"><a href="#fieldset_0-10_10-1">EnRCTX</a></td><td class="lr" colspan="1"><a href="#fieldset_0-9_9">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-8_8-1">SED</a></td><td class="lr" colspan="1"><a href="#fieldset_0-7_7-1">ITD</a></td><td class="lr" colspan="1"><a href="#fieldset_0-6_6-1">nAA</a></td><td class="lr" colspan="1"><a href="#fieldset_0-5_5-1">CP15BEN</a></td><td class="lr" colspan="1"><a href="#fieldset_0-4_4-1">SA0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-3_3">SA</a></td><td class="lr" colspan="1"><a href="#fieldset_0-2_2">C</a></td><td class="lr" colspan="1"><a href="#fieldset_0-1_1">A</a></td><td class="lr" colspan="1"><a href="#fieldset_0-0_0">M</a></td></tr></tbody></table><h4 id="fieldset_0-63_63-1">TIDCP, bit [63]<span class="condition"><br/>When FEAT_TIDCP1 is implemented and HCR_EL2.E2H == 1:
                        </span></h4><div class="field">
      <p>Trap <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> functionality. Traps EL0 accesses to the encodings reserved for <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> functionality to EL2.</p>
    <table class="valuetable"><tr><th>TIDCP</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>No instructions accessing the System register or System instruction spaces are trapped by this mechanism.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td><p>If HCR_EL2.TGE==0, no instructions accessing the System register or System instruction spaces are trapped by this mechanism.</p>
<p>If HCR_EL2.TGE==1, instructions accessing the following System register or System instruction spaces are trapped to EL2 by this mechanism:</p>
<ul>
<li>
<p>In AArch64 state, EL0 access to the encodings in the following reserved encoding spaces are trapped and reported using EC syndrome <span class="hexnumber">0x18</span>:</p>
<ul>
<li>
<p><span class="arm-defined-word">IMPLEMENTATION DEFINED</span> System instructions, which are accessed using SYS and SYSL, with CRn == {11, 15}.</p>

</li><li>
<p><span class="arm-defined-word">IMPLEMENTATION DEFINED</span> System registers, which are accessed using MRS and MSR with the <a href="AArch64-s3_op1_cn_cm_op2.html">S3_&lt;op1&gt;_&lt;Cn&gt;_&lt;Cm&gt;_&lt;op2&gt;</a> register name.</p>

</li></ul>

</li><li>
<p>In AArch32 state, EL0 MCR and MRC access to the following encodings are trapped and reported using EC syndrome <span class="hexnumber">0x03</span>:</p>
<ul>
<li>
<p>All coproc==p15, CRn==c9, opc1 == {0-7}, CRm == {c0-c2, c5-c8}, opc2 == {0-7}.</p>

</li><li>
<p>All coproc==p15, CRn==c10, opc1 =={0-7}, CRm == {c0, c1, c4, c8}, opc2 == {0-7}.</p>

</li><li>
<p>All coproc==p15, CRn==c11, opc1=={0-7}, CRm == {c0-c8, c15}, opc2 == {0-7}.</p>

</li></ul>

</li></ul></td></tr></table>
      <p>If <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE == <span class="binarynumber">0b0</span>, the field is IGNORED for all purposes other than direct reads and writes of the register.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-63_63-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-62_62-1">SPINTMASK, bit [62]<span class="condition"><br/>When FEAT_NMI is implemented:
                        </span></h4><div class="field">
      <p>SP Interrupt Mask enable. When SCTLR_EL2.NMI is 1, controls whether PSTATE.SP acts as an interrupt mask, and controls the value of PSTATE.ALLINT on taking an exception to EL2.</p>
    <table class="valuetable"><tr><th>SPINTMASK</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td><p>Does not cause PSTATE.SP to mask interrupts.</p>
<p>PSTATE.ALLINT is set to 1 on taking an exception to EL2.</p></td></tr><tr><td class="bitfield">0b1</td><td><p>When PSTATE.SP is 1 and execution is at EL2, an IRQ or FIQ interrupt that is targeted to EL2 is masked regardless of any denotion of Superpriority.</p>
<p>PSTATE.ALLINT is set to 0 on taking an exception to EL2.</p></td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-62_62-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-61_61-1">NMI, bit [61]<span class="condition"><br/>When FEAT_NMI is implemented:
                        </span></h4><div class="field">
      <p>Non-maskable Interrupt enable.</p>
    <table class="valuetable"><tr><th>NMI</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>This control does not affect interrupt masking behavior.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td><p>This control enables all of the following:</p>
<ul>
<li>
<p>The use of the PSTATE.ALLINT interrupt mask.</p>

</li><li>
<p>IRQ and FIQ interrupts to have Superpriority as an additional attribute.</p>

</li><li>
<p>PSTATE.SP to be used as an interrupt mask.</p>

</li></ul></td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><h4 id="fieldset_0-61_61-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-60_60-1">EnTP2, bit [60]<span class="condition"><br/>When FEAT_SME is implemented and HCR_EL2.E2H == 1:
                        </span></h4><div class="field">
      <p>Traps instructions executed at EL0 that access <a href="AArch64-tpidr2_el0.html">TPIDR2_EL0</a> to EL2 when EL2 is implemented and enabled for the current Security state. The exception is reported using ESR_ELx.EC value <span class="hexnumber">0x18</span>.</p>
    <table class="valuetable"><tr><th>EnTP2</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>This control causes execution of these instructions at EL0 to be trapped.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>This control does not cause execution of any instructions to be trapped.</p>
        </td></tr></table>
      <p>If <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE == <span class="binarynumber">0b0</span>, the field is IGNORED for all purposes other than direct reads and writes of the register.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-60_60-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-59_59-1">TCSO, bit [59]<span class="condition"><br/>When FEAT_MTE_STORE_ONLY is implemented:
                        </span></h4><div class="field">
      <p>Tag Checking Store Only.</p>
    <table class="valuetable"><tr><th>TCSO</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>This field has no effect on Tag checking.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Load instructions executed in EL2 are Tag Unchecked.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-59_59-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-58_58-1">TCSO0, bit [58]<span class="condition"><br/>When FEAT_MTE_STORE_ONLY is implemented and HCR_EL2.E2H == 1:
                        </span></h4><div class="field">
      <p>Tag Checking Store Only in EL0.</p>
    <table class="valuetable"><tr><th>TCSO0</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>This field has no effect on Tag checking.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Load instructions executed in EL0 are Tag Unchecked.</p>
        </td></tr></table>
      <p>If <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE == <span class="binarynumber">0b0</span>, the field is IGNORED for all purposes other than direct reads and writes of the register.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-58_58-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-57_57-1">EPAN, bit [57]<span class="condition"><br/>When FEAT_PAN3 is implemented and HCR_EL2.E2H == 1:
                        </span></h4><div class="field">
      <p>Enhanced Privileged Access Never. When PSTATE.PAN is 1, determines whether an EL2 data access to a page with EL0 instruction access permission generates a Permission fault as a result of the Privileged Access Never mechanism.</p>
    <table class="valuetable"><tr><th>EPAN</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>No additional Permission faults are generated by this mechanism.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td><p>An EL2 data access to a page with stage 1 EL0 data access permission or stage 1 EL0 instruction access permission generates a Permission fault.</p>
<p>Any speculative data accesses that would generate a Permission fault as a result of PSTATE.PAN = 1 if the accesses were not speculative, will not cause an allocation into a cache.</p></td></tr></table><p>If <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE == <span class="binarynumber">0b0</span>, the field is IGNORED for all purposes other than direct reads and writes of the register.</p>
<p>This bit is permitted to be cached in a TLB.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-57_57-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-56_56-1">EnALS, bit [56]<span class="condition"><br/>When FEAT_LS64 is implemented and HCR_EL2.E2H == 1:
                        </span></h4><div class="field">
      <p>Traps execution of an LD64B or ST64B instruction at EL0 to EL2.</p>
    <table class="valuetable"><tr><th>EnALS</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Execution of an LD64B or ST64B instruction at EL0 is trapped to EL2.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>This control does not cause any instructions to be trapped.</p>
        </td></tr></table><p>If <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE == <span class="binarynumber">0b0</span>, the field is IGNORED for all purposes other than direct reads and writes of the register.</p>
<p>A trap of an LD64B or ST64B instruction is reported using an ESR_ELx.EC value of <span class="hexnumber">0x0A</span>, with an ISS code of <span class="hexnumber">0x0000002</span>.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-56_56-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-55_55-1">EnAS0, bit [55]<span class="condition"><br/>When FEAT_LS64_ACCDATA is implemented and HCR_EL2.E2H == 1:
                        </span></h4><div class="field">
      <p>Traps execution of an ST64BV0 instruction at EL0 to EL2.</p>
    <table class="valuetable"><tr><th>EnAS0</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Execution of an ST64BV0 instruction at EL0 is trapped to EL2.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>This control does not cause any instructions to be trapped.</p>
        </td></tr></table><p>If <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE == <span class="binarynumber">0b0</span>, the field is IGNORED for all purposes other than direct reads and writes of the register.</p>
<p>A trap of an ST64BV0 instruction is reported using an ESR_ELx.EC value of <span class="hexnumber">0x0A</span>, with an ISS code of <span class="hexnumber">0x0000001</span>.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-55_55-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-54_54-1">EnASR, bit [54]<span class="condition"><br/>When FEAT_LS64_V is implemented and HCR_EL2.E2H == 1:
                        </span></h4><div class="field">
      <p>Traps execution of an ST64BV instruction at EL0 to EL2.</p>
    <table class="valuetable"><tr><th>EnASR</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Execution of an ST64BV instruction at EL0 is trapped to EL2.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>This control does not cause any instructions to be trapped.</p>
        </td></tr></table><p>If <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE == <span class="binarynumber">0b0</span>, the field is IGNORED for all purposes other than direct reads and writes of the register.</p>
<p>A trap of an ST64BV instruction is reported using an ESR_ELx.EC value of <span class="hexnumber">0x0A</span>, with an ISS code of <span class="hexnumber">0x0000000</span>.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-54_54-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-53_53-1">TME, bit [53]<span class="condition"><br/>When FEAT_TME is implemented:
                        </span></h4><div class="field">
      <p>Enables the Transactional Memory Extension at EL2.</p>
    <table class="valuetable"><tr><th>TME</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Any attempt to execute a TSTART instruction at EL2 is trapped, unless <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TME or <a href="AArch64-scr_el3.html">SCR_EL3</a>.TME causes TSTART instructions to be <span class="arm-defined-word">UNDEFINED</span> at EL2.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>This control does not cause any TSTART instruction to be trapped.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-53_53-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-52_52-1">TME0, bit [52]<span class="condition"><br/>When FEAT_TME is implemented and HCR_EL2.E2H == 1:
                        </span></h4><div class="field">
      <p>Enables the Transactional Memory Extension at EL0.</p>
    <table class="valuetable"><tr><th>TME0</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Any attempt to execute a TSTART instruction at EL0 is trapped to EL2, unless <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TME or <a href="AArch64-scr_el3.html">SCR_EL3</a>.TME causes TSTART instructions to be <span class="arm-defined-word">UNDEFINED</span> at EL0.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>This control does not cause any TSTART instruction to be trapped.</p>
        </td></tr></table>
      <p>If <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE == <span class="binarynumber">0b0</span>, the field is IGNORED for all purposes other than direct reads and writes of the register.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-52_52-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-51_51-1">TMT, bit [51]<span class="condition"><br/>When FEAT_TME is implemented:
                        </span></h4><div class="field">
      <p>Forces a trivial implementation of the Transactional Memory Extension at EL2.</p>
    <table class="valuetable"><tr><th>TMT</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>This control does not cause any TSTART instruction to fail.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>When the TSTART instruction is executed at EL2, the transaction fails with a TRIVIAL failure cause.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-51_51-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-50_50-1">TMT0, bit [50]<span class="condition"><br/>When FEAT_TME is implemented and HCR_EL2.E2H == 1:
                        </span></h4><div class="field">
      <p>Forces a trivial implementation of the Transactional Memory Extension at EL0.</p>
    <table class="valuetable"><tr><th>TMT0</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>This control does not cause any TSTART instruction to fail.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>When the TSTART instruction is executed at EL0, the transaction fails with a TRIVIAL failure cause.</p>
        </td></tr></table>
      <p>If <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE == <span class="binarynumber">0b0</span>, the field is IGNORED for all purposes other than direct reads and writes of the register.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-50_50-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-49_46-1">TWEDEL, bits [49:46]<span class="condition"><br/>When FEAT_TWED is implemented and HCR_EL2.E2H == 1:
                        </span></h4><div class="field">
      <p>TWE Delay. A 4-bit unsigned number that, when SCTLR_EL2.TWEDEn is 1, encodes the minimum delay in taking a trap of WFE caused by SCTLR_EL2.nTWE as 2<sup>(TWEDEL + 8)</sup> cycles.</p>
    
      <p>If <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE == <span class="binarynumber">0b0</span>, the field is IGNORED for all purposes other than direct reads and writes of the register.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-49_46-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-45_45-1">TWEDEn, bit [45]<span class="condition"><br/>When FEAT_TWED is implemented and HCR_EL2.E2H == 1:
                        </span></h4><div class="field">
      <p>TWE Delay Enable. Enables a configurable delayed trap of the WFE instruction caused by SCTLR_EL2.nTWE.</p>
    <table class="valuetable"><tr><th>TWEDEn</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>The delay for taking a WFE trap is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span>.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>The delay for taking a WFE trap is at least the number of cycles defined in SCTLR_EL2.TWEDEL.</p>
        </td></tr></table>
      <p>If <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE == <span class="binarynumber">0b0</span>, the field is IGNORED for all purposes other than direct reads and writes of the register.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-45_45-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-44_44-1">DSSBS, bit [44]<span class="condition"><br/>When FEAT_SSBS is implemented:
                        </span></h4><div class="field">
      <p>Default PSTATE.SSBS value on Exception Entry.</p>
    <table class="valuetable"><tr><th>DSSBS</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>PSTATE.SSBS is set to 0 on an exception to EL2.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>PSTATE.SSBS is set to 1 on an exception to EL2.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>
                        On a Warm reset,
                        
      this field resets
       to an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> value.</li></ul></div><h4 id="fieldset_0-44_44-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-43_43-1">ATA, bit [43]<span class="condition"><br/>When FEAT_MTE2 is implemented:
                        </span></h4><div class="field"><p>Allocation Tag Access in EL2.</p>
<p>When <a href="AArch64-scr_el3.html">SCR_EL3</a>.ATA is 1, controls access to Allocation Tags and Tag Check operations in EL2.</p><table class="valuetable"><tr><th>ATA</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td><p>Access to Allocation Tags is prevented at EL2.</p>
<p>Memory accesses at EL2 are not subject to a Tag Check operation.</p></td></tr><tr><td class="bitfield">0b1</td><td><p>This control does not prevent access to Allocation Tags at EL2.</p>
<p>Tag Checked memory accesses at EL2 are subject to a Tag Check operation.</p>
<p>The Tag Check operation depends on the type of tag at the memory being accessed:</p>
<ul>
<li>For Allocation Tagged memory, an Allocation Tag Check operation.
</li><li>If FEAT_MTE_CANONICAL_TAGS is implemented, for Canonically Tagged memory, a Canonical Tag Check operation.
</li></ul></td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-43_43-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-42_42-1">ATA0, bit [42]<span class="condition"><br/>When FEAT_MTE2 is implemented and HCR_EL2.E2H == 1:
                        </span></h4><div class="field"><p>Allocation Tag Access in EL0.</p>
<p>When <a href="AArch64-scr_el3.html">SCR_EL3</a>.ATA is 1, controls access to Allocation Tags and Tag Check operations in EL0.</p><table class="valuetable"><tr><th>ATA0</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td><p>Access to Allocation Tags is prevented at EL0.</p>
<p>Memory accesses at EL0 are not subject to a Tag Check operation.</p></td></tr><tr><td class="bitfield">0b1</td><td><p>This control does not prevent access to Allocation Tags at EL0.</p>
<p>Tag Checked memory accesses at EL0 are subject to a Tag Check operation.</p>
<p>The Tag Check operation depends on the type of tag at the memory being accessed:</p>
<ul>
<li>For Allocation Tagged memory, an Allocation Tag Check operation.
</li><li>If FEAT_MTE_CANONICAL_TAGS is implemented, for Canonically Tagged memory, a Canonical Tag Check operation.
</li></ul></td></tr></table><p>If <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE == <span class="binarynumber">0b0</span>, the field is IGNORED for all purposes other than direct reads and writes of the register.</p>
<div class="note"><span class="note-header">Note</span><p>Software may change this control bit on a context switch.</p></div><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-42_42-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-41_40-1">TCF, bits [41:40]<span class="condition"><br/>When FEAT_MTE2 is implemented:
                        </span></h4><div class="field">
      <p>Tag Check Fault in EL2. Controls the effect of Tag Check Faults due to Loads and Stores in EL2.</p>
    <table class="valuetable"><tr><th>TCF</th><th>Meaning</th><th>Applies when</th></tr><tr><td class="bitfield">0b00</td><td>
          <p>Tag Check Faults have no effect on the PE.</p>
        </td></tr><tr><td class="bitfield">0b01</td><td>
          <p>Tag Check Faults cause a synchronous exception.</p>
        </td></tr><tr><td class="bitfield">0b10</td><td>
          <p>Tag Check Faults are asynchronously accumulated.</p>
        </td></tr><tr><td class="bitfield">0b11</td><td>
          <p>Tag Check Faults cause a synchronous exception on reads, and are asynchronously accumulated on writes.</p>
        </td><td>When FEAT_MTE3 is implemented</td></tr></table>
      <p>If FEAT_MTE3 is not implemented, the value <span class="binarynumber">0b11</span> is reserved.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-41_40-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-39_38-1">TCF0, bits [39:38]<span class="condition"><br/>When FEAT_MTE2 is implemented and HCR_EL2.E2H == 1:
                        </span></h4><div class="field">
      <p>Tag Check Fault in EL0. Controls the effect of Tag Check Faults due to Loads and Stores in EL0.</p>
    <table class="valuetable"><tr><th>TCF0</th><th>Meaning</th><th>Applies when</th></tr><tr><td class="bitfield">0b00</td><td>
          <p>Tag Check Faults have no effect on the PE.</p>
        </td></tr><tr><td class="bitfield">0b01</td><td>
          <p>Tag Check Faults cause a synchronous exception.</p>
        </td></tr><tr><td class="bitfield">0b10</td><td>
          <p>Tag Check Faults are asynchronously accumulated.</p>
        </td></tr><tr><td class="bitfield">0b11</td><td>
          <p>Tag Check Faults cause a synchronous exception on reads, and are asynchronously accumulated on writes.</p>
        </td><td>When FEAT_MTE3 is implemented</td></tr></table><p>If <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE == <span class="binarynumber">0b0</span>, the field is IGNORED for all purposes other than direct reads and writes of the register.</p>
<p>If FEAT_MTE3 is not implemented, the value <span class="binarynumber">0b11</span> is reserved.</p>
<div class="note"><span class="note-header">Note</span><p>Software may change this control bit on a context switch.</p></div><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-39_38-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-37_37-1">ITFSB, bit [37]<span class="condition"><br/>When FEAT_MTE2 is implemented:
                        </span></h4><div class="field">
      <p>When synchronous exceptions are not being generated by Tag Check Faults, this field controls whether on exception entry into EL2, all Tag Check Faults due to instructions executed before exception entry, that are reported asynchronously, are synchronized into <a href="AArch64-tfsre0_el1.html">TFSRE0_EL1</a>, <a href="AArch64-tfsr_el1.html">TFSR_EL1</a> and <a href="AArch64-tfsr_el2.html">TFSR_EL2</a> registers.</p>
    <table class="valuetable"><tr><th>ITFSB</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Tag Check Faults are not synchronized on entry to EL2.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Tag Check Faults are synchronized on entry to EL2.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-37_37-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-36_36-1">BT, bit [36]<span class="condition"><br/>When FEAT_BTI is implemented:
                        </span></h4><div class="field"><p>PAC Branch Type compatibility at EL2.</p>
<p>When <a href="AArch64-hcr_el2.html">HCR_EL2</a>.{E2H, TGE} == {1, 1}, this bit is named BT1.</p><table class="valuetable"><tr><th>BT</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>When the PE is executing at EL2, PACIASP and PACIBSP are compatible with PSTATE.BTYPE == <span class="binarynumber">0b11</span>.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>When the PE is executing at EL2, PACIASP and PACIBSP are not compatible with PSTATE.BTYPE == <span class="binarynumber">0b11</span>.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-36_36-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-35_35-1">BT0, bit [35]<span class="condition"><br/>When FEAT_BTI is implemented and HCR_EL2.E2H == 1:
                        </span></h4><div class="field">
      <p>PAC Branch Type compatibility at EL0.</p>
    <table class="valuetable"><tr><th>BT0</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>When the PE is executing at EL0, PACIASP and PACIBSP are compatible with PSTATE.BTYPE == <span class="binarynumber">0b11</span>.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>When the PE is executing at EL0, PACIASP and PACIBSP are not compatible with PSTATE.BTYPE == <span class="binarynumber">0b11</span>.</p>
        </td></tr></table>
      <p>If <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE == <span class="binarynumber">0b0</span>, the field is IGNORED for all purposes other than direct reads and writes of the register.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-35_35-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-34_34">Bit [34]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-33_33-1">MSCEn, bit [33]<span class="condition"><br/>When FEAT_MOPS is implemented and HCR_EL2.E2H == 1:
                        </span></h4><div class="field">
      <p>Memory Copy and Memory Set instructions Enable. Enables execution of the Memory Copy and Memory Set instructions at EL0.</p>
    <table class="valuetable"><tr><th>MSCEn</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Execution of the Memory Copy and Memory Set instructions is <span class="arm-defined-word">UNDEFINED</span> at EL0.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>This control does not cause any instructions to be <span class="arm-defined-word">UNDEFINED</span>.</p>
        </td></tr></table><p>If <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE == <span class="binarynumber">0b0</span>, the field is IGNORED for all purposes other than direct reads and writes of the register.</p>
<p>When <span class="xref">FEAT_MOPS</span> is implemented and <a href="AArch64-hcr_el2.html">HCR_EL2</a>.{E2H, TGE} is not {1, 1}, the Effective value of this bit is <span class="binarynumber">0b1</span>.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-33_33-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-32_32-1">CMOW, bit [32]<span class="condition"><br/>When FEAT_CMOW is implemented and HCR_EL2.E2H == 1:
                        </span></h4><div class="field"><p>Controls cache maintenance instruction permission for the following instructions executed at EL0.</p>
<ul>
<li><a href="AArch64-ic-ivau.html">IC IVAU</a>, <a href="AArch64-dc-civac.html">DC CIVAC</a>, <a href="AArch64-dc-cigdvac.html">DC CIGDVAC</a> and <a href="AArch64-dc-cigvac.html">DC CIGVAC</a>.
</li></ul><table class="valuetable"><tr><th>CMOW</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>These instructions executed at EL0  with stage 1 read permission, but without stage 1 write permission, do not generate a stage 1 permission fault.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>If enabled as a result of <a href="AArch64-sctlr_el2.html">SCTLR_EL2</a>.UCI==1, these instructions executed at EL0  with stage 1 read permission, but without stage 1 write permission, generate a stage 1 permission fault.</p>
        </td></tr></table><p>If <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE == <span class="binarynumber">0b0</span>, the field is IGNORED for all purposes other than direct reads and writes of the register.</p>
<p>For this control, stage 1 has write permission if all of the following apply:</p>
<ul>
<li>AP[2] is 0 or DBM is 1 in the stage 1 descriptor.
</li><li>Where APTable is in use, APTable[1] is 0 for all levels of the translation table.
</li></ul>
<p>This bit is permitted to be cached in a TLB.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-32_32-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-31_31-1">EnIA, bit [31]<span class="condition"><br/>When FEAT_PAuth is implemented:
                        </span></h4><div class="field">
      <p>Controls enabling of pointer authentication of instruction addresses, using the APIAKey_EL1 key, in the EL2 or EL2&amp;0 translation regime.</p>
    <table class="valuetable"><tr><th>EnIA</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Pointer authentication of instruction addresses, using the APIAKey_EL1 key, is not enabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Pointer authentication of instruction addresses, using the APIAKey_EL1 key, is enabled.</p>
        </td></tr></table>
      <div class="note"><span class="note-header">Note</span>
        <p>This field controls the behavior of the AddPACIA and AuthIA pseudocode functions. Specifically, when the field is 1, AddPACIA returns a copy of a pointer to which a pointer authentication code has been added, and AuthIA returns an authenticated copy of a pointer. When the field is 0, both of these functions are NOP.</p>
      </div>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-31_31-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-30_30-1">EnIB, bit [30]<span class="condition"><br/>When FEAT_PAuth is implemented:
                        </span></h4><div class="field">
      <p>Controls enabling of pointer authentication of instruction addresses, using the APIBKey_EL1 key, in the EL2 or EL2&amp;0 translation regime.</p>
    <table class="valuetable"><tr><th>EnIB</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Pointer authentication of instruction addresses, using the APIBKey_EL1 key, is not enabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Pointer authentication of instruction addresses, using the APIBKey_EL1 key, is enabled.</p>
        </td></tr></table>
      <div class="note"><span class="note-header">Note</span>
        <p>This field controls the behavior of the AddPACIB and AuthIB pseudocode functions. Specifically, when the field is 1, AddPACIB returns a copy of a pointer to which a pointer authentication code has been added, and AuthIB returns an authenticated copy of a pointer. When the field is 0, both of these functions are NOP.</p>
      </div>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-30_30-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-29_29-1">LSMAOE, bit [29]<span class="condition"><br/>When FEAT_LSMAOC is implemented and HCR_EL2.E2H == 1:
                        </span></h4><div class="field">
      <p>Load Multiple and Store Multiple Atomicity and Ordering Enable.</p>
    <table class="valuetable"><tr><th>LSMAOE</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>For all memory accesses at EL0, A32 and T32 Load Multiple and Store Multiple can have an interrupt taken during the sequence memory accesses, and the memory accesses are not required to be ordered.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>The ordering and interrupt behavior of A32 and T32 Load Multiple and Store Multiple at EL0 is as defined for Armv8.0.</p>
        </td></tr></table><p>If <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE == <span class="binarynumber">0b0</span>, the field is IGNORED for all purposes other than direct reads and writes of the register.</p>
<p>This bit is permitted to be cached in a TLB.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-29_29-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES1</span>.</p>
    </div><h4 id="fieldset_0-28_28-1">nTLSMD, bit [28]<span class="condition"><br/>When FEAT_LSMAOC is implemented and HCR_EL2.E2H == 1:
                        </span></h4><div class="field">
      <p>No Trap Load Multiple and Store Multiple to Device-nGRE/Device-nGnRE/Device-nGnRnE memory.</p>
    <table class="valuetable"><tr><th>nTLSMD</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>All memory accesses by A32 and T32 Load Multiple and Store Multiple at EL0 that are marked at stage 1 as Device-nGRE/Device-nGnRE/Device-nGnRnE memory are trapped and generate a stage 1 Alignment fault.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>All memory accesses by A32 and T32 Load Multiple and Store Multiple at EL0 that are marked at stage 1 as Device-nGRE/Device-nGnRE/Device-nGnRnE memory are not trapped.</p>
        </td></tr></table><p>If <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE == <span class="binarynumber">0b0</span>, the field is IGNORED for all purposes other than direct reads and writes of the register.</p>
<p>This bit is permitted to be cached in a TLB.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-28_28-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES1</span>.</p>
    </div><h4 id="fieldset_0-27_27-1">EnDA, bit [27]<span class="condition"><br/>When FEAT_PAuth is implemented:
                        </span></h4><div class="field">
      <p>Controls enabling of pointer authentication of instruction addresses, using the APDAKey_EL1 key, in the EL2 or EL2&amp;0 translation regime.</p>
    <table class="valuetable"><tr><th>EnDA</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Pointer authentication of data addresses, using the APDAKey_EL1 key, is not enabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Pointer authentication of data addresses, using the APDAKey_EL1 key, is enabled.</p>
        </td></tr></table>
      <div class="note"><span class="note-header">Note</span>
        <p>This field controls the behavior of the AddPACDA and AuthDA pseudocode functions. Specifically, when the field is 1, AddPACDA returns a copy of a pointer to which a pointer authentication code has been added, and AuthDA returns an authenticated copy of a pointer. When the field is 0, both of these functions are NOP.</p>
      </div>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-27_27-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-26_26-1">UCI, bit [26]<span class="condition"><br/>When HCR_EL2.E2H == 1:
                        </span></h4><div class="field"><p>Traps execution of cache maintenance instructions at EL0 to EL2, from AArch64 state only. This applies to <a href="AArch64-dc-cvau.html">DC CVAU</a>, <a href="AArch64-dc-civac.html">DC CIVAC</a>, <a href="AArch64-dc-cvac.html">DC CVAC</a>, <a href="AArch64-dc-cvap.html">DC CVAP</a>, and <a href="AArch64-ic-ivau.html">IC IVAU</a>.</p>
<p>If <span class="xref">FEAT_DPB2</span> is implemented, this trap also applies to <a href="AArch64-dc-cvadp.html">DC CVADP</a>.</p>
<p>If <span class="xref">FEAT_MTE</span> is implemented, this trap also applies to <a href="AArch64-dc-cigvac.html">DC CIGVAC</a>, <a href="AArch64-dc-cigdvac.html">DC CIGDVAC</a>, <a href="AArch64-dc-cgvac.html">DC CGVAC</a>, <a href="AArch64-dc-cgdvac.html">DC CGDVAC</a>, <a href="AArch64-dc-cgvap.html">DC CGVAP</a>, and <a href="AArch64-dc-cgdvap.html">DC CGDVAP</a>.</p>
<p>If <span class="xref">FEAT_DPB2</span> and <span class="xref">FEAT_MTE</span> are implemented, this trap also applies to <a href="AArch64-dc-cgvadp.html">DC CGVADP</a> and <a href="AArch64-dc-cgdvadp.html">DC CGDVADP</a>.</p><table class="valuetable"><tr><th>UCI</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Any attempt to execute an instruction that this trap applies to at EL0 using AArch64 is trapped to EL2.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>This control does not cause any instructions to be trapped.</p>
        </td></tr></table><p>If <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE == <span class="binarynumber">0b0</span>, the field is IGNORED for all purposes other than direct reads and writes of the register.</p>
<p>If the Point of Coherency is before any level of data cache, it is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> whether the execution of any data or unified cache clean, or clean and invalidate instruction that operates by VA to the point of coherency can be trapped when the value of this control is 1.</p>
<p>If the Point of Unification is before any level of data cache, it is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> whether the execution of any data or unified cache clean by VA to the Point of Unification instruction can be trapped when the value of this control is 1.</p>
<p>If the Point of Unification is before any level of instruction cache, it is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> whether the execution of any instruction cache invalidate by VA to the Point of Unification instruction can be trapped when the value of this control is 1.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-26_26-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-25_25">EE, bit [25]</h4><div class="field">
      <p>Endianness of data accesses at EL2, stage 1 translation table walks in the EL2 or EL2&amp;0 translation regime, and stage 2 translation table walks in the EL1&amp;0 translation regime.</p>
    <table class="valuetable"><tr><th>EE</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Explicit data accesses at EL2, stage 1 translation table walks in the EL2 or EL2&amp;0 translation regime, and stage 2 translation table walks in the EL1&amp;0 translation regime are little-endian.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Explicit data accesses at EL2, stage 1 translation table walks in the EL2 or EL2&amp;0 translation regime, and stage 2 translation table walks in the EL1&amp;0 translation regime are big-endian.</p>
        </td></tr></table><p>If an implementation does not provide Big-endian support at Exception levels higher than EL0, this bit is <span class="arm-defined-word">RES0</span>.</p>
<p>If an implementation does not provide Little-endian support at Exception levels higher than EL0, this bit is <span class="arm-defined-word">RES1</span>.</p>
<p>The EE bit is permitted to be cached in a TLB.</p><p>The reset behavior of this field is:</p><ul><li>
                        On a Warm reset,
                        
      this field resets
       to an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> value.</li></ul></div><h4 id="fieldset_0-24_24-1">E0E, bit [24]<span class="condition"><br/>When HCR_EL2.E2H == 1:
                        </span></h4><div class="field">
      <p>Endianness of data accesses at EL0.</p>
    <table class="valuetable"><tr><th>E0E</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Explicit data accesses at EL0 are little-endian.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Explicit data accesses at EL0 are big-endian.</p>
        </td></tr></table><p>If <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE == <span class="binarynumber">0b0</span>, the field is IGNORED for all purposes other than direct reads and writes of the register.</p>
<p>If an implementation only supports Little-endian accesses at EL0, then this bit is <span class="arm-defined-word">RES0</span>. This option is not permitted when SCTLR_EL1.EE is <span class="arm-defined-word">RES1</span>.</p>
<p>If an implementation only supports Big-endian accesses at EL0, then this bit is <span class="arm-defined-word">RES1</span>. This option is not permitted when SCTLR_EL1.EE is <span class="arm-defined-word">RES0</span>.</p>
<p>This bit has no effect on the endianness of <span class="instruction">LDTR</span>, <span class="instruction">LDTRH</span>, <span class="instruction">LDTRSH</span>, <span class="instruction">LDTRSW</span>, <span class="instruction">STTR</span>, and <span class="instruction">STTRH</span> instructions executed at EL1.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-24_24-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-23_23-1">SPAN, bit [23]<span class="condition"><br/>When HCR_EL2.E2H == 1:
                        </span></h4><div class="field">
      <p>Set Privileged Access Never, on taking an exception to EL2.</p>
    <table class="valuetable"><tr><th>SPAN</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>PSTATE.PAN is set to 1 on taking an exception to EL2.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>The value of PSTATE.PAN is left unchanged on taking an exception to EL2.</p>
        </td></tr></table>
      <p>If <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE == <span class="binarynumber">0b0</span>, the field is IGNORED for all purposes other than direct reads and writes of the register.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-23_23-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES1</span>.</p>
    </div><h4 id="fieldset_0-22_22-1">EIS, bit [22]<span class="condition"><br/>When FEAT_ExS is implemented:
                        </span></h4><div class="field">
      <p>Exception entry is a context synchronization event.</p>
    <table class="valuetable"><tr><th>EIS</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>The taking of an exception to EL2 is not a context synchronization event.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>The taking of an exception to EL2 is a context synchronization event.</p>
        </td></tr></table><p>If SCTLR_EL2.EIS is set to <span class="binarynumber">0b0</span>:</p>
<ul>
<li>Indirect writes to <a href="AArch64-esr_el2.html">ESR_EL2</a>, <a href="AArch64-far_el2.html">FAR_EL2</a>, <a href="AArch64-spsr_el2.html">SPSR_EL2</a>, <a href="AArch64-elr_el2.html">ELR_EL2</a>, and <a href="AArch64-hpfar_el2.html">HPFAR_EL2</a> are synchronized on exception entry to EL2, so that a direct read of the register after exception entry sees the indirectly written value caused by the exception entry.
</li><li>Memory transactions, including instruction fetches, from an Exception level always use the translation resources associated with that translation regime.
</li><li>Exception Catch debug events are synchronous debug events.
</li><li>DCPS* and DRPS instructions are context synchronization events.
</li></ul>
<p>The following are not affected by the value of SCTLR_EL2.EIS:</p>
<ul>
<li>Changes to the PSTATE information on entry to EL2.
</li><li>Behavior of accessing the banked copies of the stack pointer using the SP register name for loads, stores, and data processing instructions.
</li><li>Exit from Debug state.
</li></ul><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-22_22-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES1</span>.</p>
    </div><h4 id="fieldset_0-21_21-1">IESB, bit [21]<span class="condition"><br/>When FEAT_IESB is implemented:
                        </span></h4><div class="field">
      <p>Implicit Error Synchronization event enable.</p>
    <table class="valuetable"><tr><th>IESB</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Disabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td><p>An implicit error synchronization event is added:</p>
<ul>
<li>At each exception taken to EL2.
</li><li>Before the operational pseudocode of each <span class="instruction">ERET</span> instruction executed at EL2.
</li></ul></td></tr></table>
      <p>When the PE is in Debug state, the effect of this field is <span class="arm-defined-word">CONSTRAINED UNPREDICTABLE</span>, and its Effective value might be 0 or 1 regardless of the value of the field. If the Effective value of the field is 1, then an implicit error synchronization event is added after each <span class="instruction">DCPSx</span> instruction taken to EL2 and before each <span class="instruction">DRPS</span> instruction executed at EL2, in addition to the other cases where it is added.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-21_21-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-20_20-1">TSCXT, bit [20]<span class="condition"><br/>When (FEAT_CSV2_2 is implemented or FEAT_CSV2_1p2 is implemented) and HCR_EL2.E2H == 1:
                        </span></h4><div class="field">
      <p>Trap EL0 Access to the SCXTNUM_EL0 register, when EL0 is using AArch64.</p>
    <table class="valuetable"><tr><th>TSCXT</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>EL0 access to <a href="AArch64-scxtnum_el0.html">SCXTNUM_EL0</a> is not disabled by this mechanism.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>EL0 access to <a href="AArch64-scxtnum_el0.html">SCXTNUM_EL0</a> is disabled, causing an exception to EL2, and the <a href="AArch64-scxtnum_el0.html">SCXTNUM_EL0</a> value is treated as 0.</p>
        </td></tr></table>
      <p>If <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE == <span class="binarynumber">0b0</span>, the field is IGNORED for all purposes other than direct reads and writes of the register.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-20_20-2"><span class="condition"><br/>When FEAT_CSV2_2 is not implemented, FEAT_CSV2_1p2 is not implemented, HCR_EL2.E2H == 1 and HCR_EL2.TGE == 1:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES1</span>.</p>
    </div><h4 id="fieldset_0-20_20-3"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-19_19">WXN, bit [19]</h4><div class="field">
      <p>Write permission implies XN (Execute-never). For the EL2 or EL2&amp;0 translation regime, this bit can force all memory regions that are writable to be treated as XN.</p>
    <table class="valuetable"><tr><th>WXN</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>This control has no effect on memory access permissions.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Any region that is writable in the EL2 or EL2&amp;0 translation regime is forced to XN for accesses from software executing at EL2.</p>
        </td></tr></table><p>This bit applies only when SCTLR_EL2.M bit is set.</p>
<p>The WXN bit is permitted to be cached in a TLB.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-18_18-1">nTWE, bit [18]<span class="condition"><br/>When HCR_EL2.E2H == 1:
                        </span></h4><div class="field">
      <p>Traps execution of WFE instructions at EL0 to EL2, from both Execution states.</p>
    <table class="valuetable"><tr><th>nTWE</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Any attempt to execute a WFE instruction at EL0 is trapped to EL2, if the instruction would otherwise have caused the PE to enter a low-power state.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>This control does not cause any instructions to be trapped.</p>
        </td></tr></table><p>If <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE == <span class="binarynumber">0b0</span>, the field is IGNORED for all purposes other than direct reads and writes of the register.</p>
<p>In AArch32 state, the attempted execution of a conditional WFE instruction is only trapped if the instruction passes its condition code check.</p>
<div class="note"><span class="note-header">Note</span><p>Since a WFE or WFI can complete at any time, even without a Wakeup event, the traps on WFE of WFI are not guaranteed to be taken, even if the WFE or WFI is executed when there is no Wakeup event. The only guarantee is that if the instruction does not complete in finite time in the absence of a Wakeup event, the trap will be taken.</p></div><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-18_18-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES1</span>.</p>
    </div><h4 id="fieldset_0-17_17">Bit [17]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-16_16-1">nTWI, bit [16]<span class="condition"><br/>When HCR_EL2.E2H == 1:
                        </span></h4><div class="field">
      <p>Traps execution of WFI instructions at EL0 to EL2, from both Execution states.</p>
    <table class="valuetable"><tr><th>nTWI</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Any attempt to execute a WFI instruction at EL0 is trapped EL2, if the instruction would otherwise have caused the PE to enter a low-power state.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>This control does not cause any instructions to be trapped.</p>
        </td></tr></table><p>If <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE == <span class="binarynumber">0b0</span>, the field is IGNORED for all purposes other than direct reads and writes of the register.</p>
<p>In AArch32 state, the attempted execution of a conditional WFI instruction is only trapped if the instruction passes its condition code check.</p>
<div class="note"><span class="note-header">Note</span><p>Since a WFE or WFI can complete at any time, even without a Wakeup event, the traps on WFE of WFI are not guaranteed to be taken, even if the WFE or WFI is executed when there is no Wakeup event. The only guarantee is that if the instruction does not complete in finite time in the absence of a Wakeup event, the trap will be taken.</p></div><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-16_16-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES1</span>.</p>
    </div><h4 id="fieldset_0-15_15-1">UCT, bit [15]<span class="condition"><br/>When HCR_EL2.E2H == 1:
                        </span></h4><div class="field">
      <p>Traps EL0 accesses to the <a href="AArch64-ctr_el0.html">CTR_EL0</a> to EL2, from AArch64 state only.</p>
    <table class="valuetable"><tr><th>UCT</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Accesses to the <a href="AArch64-ctr_el0.html">CTR_EL0</a> from EL0 using AArch64 are trapped to EL2.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>This control does not cause any instructions to be trapped.</p>
        </td></tr></table>
      <p>If <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE == <span class="binarynumber">0b0</span>, the field is IGNORED for all purposes other than direct reads and writes of the register.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-15_15-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-14_14-1">DZE, bit [14]<span class="condition"><br/>When HCR_EL2.E2H == 1:
                        </span></h4><div class="field"><p>Traps execution of <a href="AArch64-dc-zva.html">DC ZVA</a> instructions at EL0 to EL2, from AArch64 state only.</p>
<p>If <span class="xref">FEAT_MTE</span> is implemented, this trap also applies to <a href="AArch64-dc-gva.html">DC GVA</a> and <a href="AArch64-dc-gzva.html">DC GZVA</a>.</p><table class="valuetable"><tr><th>DZE</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Any attempt to execute an instruction that this trap applies to at EL0 using AArch64 is trapped to EL2. Reading <a href="AArch64-dczid_el0.html">DCZID_EL0</a>.DZP from EL0 returns 1, indicating that the instructions that this trap applies to are not supported.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>This control does not cause any instructions to be trapped.</p>
        </td></tr></table>
      <p>If <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE == <span class="binarynumber">0b0</span>, the field is IGNORED for all purposes other than direct reads and writes of the register.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-14_14-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-13_13-1">EnDB, bit [13]<span class="condition"><br/>When FEAT_PAuth is implemented:
                        </span></h4><div class="field">
      <p>Controls enabling of pointer authentication of instruction addresses, using the APDBKey_EL1 key, in the EL2 or EL2&amp;0 translation regime.</p>
    <table class="valuetable"><tr><th>EnDB</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Pointer authentication of data addresses, using the APDBKey_EL1 key, is not enabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Pointer authentication of data addresses, using the APDBKey_EL1 key, is enabled.</p>
        </td></tr></table>
      <div class="note"><span class="note-header">Note</span>
        <p>This field controls the behavior of the AddPACDB and AuthDB pseudocode functions. Specifically, when the field is 1, AddPACDB returns a copy of a pointer to which a pointer authentication code has been added, and AuthDB returns an authenticated copy of a pointer. When the field is 0, both of these functions are NOP.</p>
      </div>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-13_13-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-12_12">I, bit [12]</h4><div class="field">
      <p>Instruction access Cacheability control, for accesses at EL2 and, when EL2 is enabled in the current Security state and <a href="AArch64-hcr_el2.html">HCR_EL2</a>.{E2H,TGE} == {1,1}, EL0.</p>
    <table class="valuetable"><tr><th>I</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td><p>All instruction accesses to Normal memory from EL2 are Non-cacheable for all levels of instruction and unified cache.</p>
<p>When EL2 is enabled in the current Security state and <a href="AArch64-hcr_el2.html">HCR_EL2</a>.{E2H, TGE} == {1, 1}, all instruction accesses to Normal memory from EL0 are Non-cacheable for all levels of instruction and unified cache.</p>
<p>If SCTLR_EL2.M is 0, instruction accesses from stage 1 of the EL2 or EL2&amp;0 translation regime are to Normal, Outer Shareable, Inner Non-cacheable, Outer Non-cacheable memory.</p></td></tr><tr><td class="bitfield">0b1</td><td><p>This control has no effect on the Cacheability of instruction access to Normal memory from EL2 and, when EL2 is enabled in the current Security state and <a href="AArch64-hcr_el2.html">HCR_EL2</a>.{E2H, TGE} == {1, 1}, instruction access to Normal memory from EL0.</p>
<p>If the value of SCTLR_EL2.M is 0, instruction accesses from stage 1 of the EL2 or EL2&amp;0 translation regime are to Normal, Outer Shareable, Inner Write-Through, Outer Write-Through memory.</p></td></tr></table><p>This bit has no effect on the EL3 translation regime.</p>
<p>When EL2 is disabled in the current Security state or <a href="AArch64-hcr_el2.html">HCR_EL2</a>.{E2H,TGE} != {1,1}, this bit has no effect on the EL1&amp;0 translation regime.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><h4 id="fieldset_0-11_11-1">EOS, bit [11]<span class="condition"><br/>When FEAT_ExS is implemented:
                        </span></h4><div class="field">
      <p>Exception exit is a context synchronization event.</p>
    <table class="valuetable"><tr><th>EOS</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>An exception return from EL2 is not a context synchronization event.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>An exception return from EL2 is a context synchronization event.</p>
        </td></tr></table><p>If SCTLR_EL2.EOS is set to <span class="binarynumber">0b0</span>:</p>
<ul>
<li>Memory transactions, including instruction fetches, from an Exception level always use the translation resources associated with that translation regime.
</li><li>Exception Catch debug events are synchronous debug events.
</li><li>DCPS* and DRPS instructions are context synchronization events.
</li></ul>
<p>The following are not affected by the value of SCTLR_EL2.EOS:</p>
<ul>
<li>The indirect write of the PSTATE and PC values from <a href="AArch64-spsr_el2.html">SPSR_EL2</a> and <a href="AArch64-elr_el2.html">ELR_EL2</a> on exception return is synchronized.
</li><li>Behavior of accessing the banked copies of the stack pointer using the SP register name for loads, stores, and data processing instructions.
</li><li>Exit from Debug state.
</li></ul><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-11_11-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES1</span>.</p>
    </div><h4 id="fieldset_0-10_10-1">EnRCTX, bit [10]<span class="condition"><br/>When FEAT_SPECRES is implemented and HCR_EL2.E2H == 1:
                        </span></h4><div class="field"><p>Enable EL0 access to the following System instructions:</p>
<ul>
<li>
<p><a href="AArch32-cfprctx.html">CFPRCTX</a>, <a href="AArch32-dvprctx.html">DVPRCTX</a> and <a href="AArch32-cpprctx.html">CPPRCTX</a> instructions.</p>

</li><li>
<p>If FEAT_SPECRES2 is implemented, <a href="AArch32-cosprctx.html">COSPRCTX</a>.</p>

</li><li>
<p><a href="AArch64-cfp-rctx.html">CFP RCTX</a>, <a href="AArch64-dvp-rctx.html">DVP RCTX</a> and <a href="AArch64-cpp-rctx.html">CPP RCTX</a> instructions.</p>

</li><li>
<p>If FEAT_SPECRES2 is implemented, <a href="AArch64-cpp-rctx.html">COSP RCTX</a>.</p>

</li></ul><table class="valuetable"><tr><th>EnRCTX</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>EL0 access to these instructions is disabled, and these instructions are trapped to EL1.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>EL0 access to these instructions is enabled.</p>
        </td></tr></table>
      <p>If <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE == <span class="binarynumber">0b0</span>, the field is IGNORED for all purposes other than direct reads and writes of the register.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-10_10-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-9_9">Bit [9]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-8_8-1">SED, bit [8]<span class="condition"><br/>When EL0 is capable of using AArch32 and HCR_EL2.E2H == 1:
                        </span></h4><div class="field">
      <p>SETEND instruction disable. Disables SETEND instructions at EL0 using AArch32.</p>
    <table class="valuetable"><tr><th>SED</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>SETEND instruction execution is enabled at EL0 using AArch32.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>SETEND instructions are <span class="arm-defined-word">UNDEFINED</span> at EL0 using AArch32.</p>
        </td></tr></table><p>If <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE == <span class="binarynumber">0b0</span>, the field is IGNORED for all purposes other than direct reads and writes of the register.</p>
<p>If the implementation does not support mixed-endian operation at any Exception level, this bit is <span class="arm-defined-word">RES1</span>.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-8_8-2"><span class="condition"><br/>When EL0 can only use AArch64 and HCR_EL2.E2H == 1:
                        </span></h4><div class="field">
      <p>If <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE == <span class="binarynumber">0b0</span>, the field is IGNORED for all purposes other than direct reads and writes of the register.</p>
    <p>Access to this field is <span class="access_level">RES1</span>.</p></div><h4 id="fieldset_0-8_8-3"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-7_7-1">ITD, bit [7]<span class="condition"><br/>When EL0 is capable of using AArch32 and HCR_EL2.E2H == 1:
                        </span></h4><div class="field">
      <p>IT Disable. Disables some uses of IT instructions at EL0 using AArch32.</p>
    <table class="valuetable"><tr><th>ITD</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>All IT instruction functionality is enabled at EL0 using AArch32.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td><p>Any attempt at EL0 using AArch32 to execute any of the following is <span class="arm-defined-word">UNDEFINED</span>:</p>
<ul>
<li>All encodings of the IT instruction with hw1[3:0]!=1000.
</li><li>All encodings of the subsequent instruction with the following values for hw1:<ul>
<li><span class="binarynumber">0b11xxxxxxxxxxxxxx</span>: All 32-bit instructions, and the 16-bit instructions B, UDF, SVC, LDM, and STM.
</li><li><span class="binarynumber">0b1011xxxxxxxxxxxx</span>: All instructions in <span class="xref">'Miscellaneous 16-bit instructions'</span>.
</li><li><span class="binarynumber">0b10100xxxxxxxxxxx</span>: ADD Rd, PC, #imm
</li><li><span class="binarynumber">0b01001xxxxxxxxxxx</span>: LDR Rd, [PC, #imm]
</li><li><span class="binarynumber">0b0100x1xxx1111xxx</span>: ADD Rdn, PC; CMP Rn, PC; MOV Rd, PC; BX PC; BLX PC.
</li><li><span class="binarynumber">0b010001xx1xxxx111</span>: ADD PC, Rm; CMP PC, Rm; MOV PC, Rm. This pattern also covers <span class="arm-defined-word">UNPREDICTABLE</span> cases with BLX Rn.
</li></ul>

</li></ul>
<p>These instructions are always <span class="arm-defined-word">UNDEFINED</span>, regardless of whether they would pass or fail the condition code check that applies to them as a result of being in an IT block.</p>
<p>It is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> whether the IT instruction is treated as:</p>
<ul>
<li>A 16-bit instruction, that can only be followed by another 16-bit instruction.
</li><li>The first half of a 32-bit instruction.
</li></ul>
<p>This means that, for the situations that are <span class="arm-defined-word">UNDEFINED</span>, either the second 16-bit instruction or the 32-bit instruction is <span class="arm-defined-word">UNDEFINED</span>.</p>
<p>An implementation might vary dynamically as to whether IT is treated as a 16-bit instruction or the first half of a 32-bit instruction.</p></td></tr></table><p>If <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE == <span class="binarynumber">0b0</span>, the field is IGNORED for all purposes other than direct reads and writes of the register.</p>
<p>If an instruction in an active IT block that would be disabled by this field sets this field to 1 then behavior is <span class="arm-defined-word">CONSTRAINED UNPREDICTABLE</span>. For more information see <span class="xref">'Changes to an ITD control by an instruction in an IT block'</span>.</p>
<p>ITD is optional, but if it is implemented in the SCTLR_EL2 then it must also be implemented in the <a href="AArch64-sctlr_el1.html">SCTLR_EL1</a>, <a href="AArch32-hsctlr.html">HSCTLR</a>, and <a href="AArch32-sctlr.html">SCTLR</a>.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul><p>When an implementation does not implement ITD, access to this field is <span class="access_level">RAZ/WI</span>.</p></div><h4 id="fieldset_0-7_7-2"><span class="condition"><br/>When EL0 can only use AArch64 and HCR_EL2.E2H == 1:
                        </span></h4><div class="field">
      <p>If <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE == <span class="binarynumber">0b0</span>, the field is IGNORED for all purposes other than direct reads and writes of the register.</p>
    </div><h4 id="fieldset_0-7_7-3"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-6_6-1">nAA, bit [6]<span class="condition"><br/>When FEAT_LSE2 is implemented:
                        </span></h4><div class="field"><p>Non-aligned access. This bit controls generation of Alignment faults under certain conditions at EL2, and, when EL2 is enabled in the current Security state and <a href="AArch64-hcr_el2.html">HCR_EL2</a>.{E2H, TGE} == {1, 1}, EL0.</p>
<p>The following instructions generate an Alignment fault if all bytes being accessed are not within a single 16-byte quantity, aligned to 16 bytes for access:</p>
<ul>
<li>
<p>LDAPR, LDAPRH, LDAPUR, LDAPURH, LDAPURSH, LDAPURSW, LDAR, LDARH, LDLAR, LDLARH.</p>

</li><li>
<p>STLLR, STLLRH, STLR, STLRH, STLUR, and STLURH</p>

</li></ul>
<p>If <span class="xref">FEAT_LRCPC3</span> is implemented,the following instructions generate an Alignment fault if all bytes being accessed for a single register are not within a single 16-byte quantity, aligned to 16 bytes for access:</p>
<ul>
<li>
<p>LDIAPP, STILP, the post index versions of LDAPR and the pre index versions of STLR.</p>

</li><li>
<p>If Advanced SIMD and floating-point instructions are implemented, LDAPUR (SIMD&amp;FP), LDAP1 (SIMD&amp;FP), STLUR (SIMD&amp;FP), and STL1 (SIMD&amp;FP).</p>

</li></ul><table class="valuetable"><tr><th>nAA</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Unaligned accesses by the specified instructions generate an Alignment fault.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Unaligned accesses by the specified instructions do not generate an Alignment fault.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-6_6-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-5_5-1">CP15BEN, bit [5]<span class="condition"><br/>When EL0 is capable of using AArch32 and HCR_EL2.E2H == 1:
                        </span></h4><div class="field">
      <p>System instruction memory barrier enable. Enables accesses to the DMB, DSB, and ISB System instructions in the (coproc==<span class="binarynumber">0b1111</span>) encoding space from EL0:</p>
    <table class="valuetable"><tr><th>CP15BEN</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>EL0 using AArch32: EL0 execution of the <a href="AArch32-cp15dmb.html">CP15DMB</a>, <a href="AArch32-cp15dsb.html">CP15DSB</a>, and <a href="AArch32-cp15isb.html">CP15ISB</a> instructions is <span class="arm-defined-word">UNDEFINED</span>.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>EL0 using AArch32: EL0 execution of the <a href="AArch32-cp15dmb.html">CP15DMB</a>, <a href="AArch32-cp15dsb.html">CP15DSB</a>, and <a href="AArch32-cp15isb.html">CP15ISB</a> instructions is enabled.</p>
        </td></tr></table><p>If <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE == <span class="binarynumber">0b0</span>, the field is IGNORED for all purposes other than direct reads and writes of the register.</p>
<p>CP15BEN is optional, but if it is implemented in the SCTLR_EL2 then it must also be implemented in the <a href="AArch64-sctlr_el1.html">SCTLR_EL1</a>, <a href="AArch32-hsctlr.html">HSCTLR</a>, and <a href="AArch32-sctlr.html">SCTLR</a>.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-5_5-2"><span class="condition"><br/>When EL0 can only use AArch64 and HCR_EL2.E2H == 1:
                        </span></h4><div class="field"><p>Access to this field is <span class="access_level">RES0</span>.</p></div><h4 id="fieldset_0-5_5-3"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES1</span>.</p>
    </div><h4 id="fieldset_0-4_4-1">SA0, bit [4]<span class="condition"><br/>When HCR_EL2.E2H == 1:
                        </span></h4><div class="field">
      <p>SP Alignment check enable for EL0. When set to 1, if a load or store instruction executed at EL0 uses the SP as the base address and the SP is not aligned to a 16-byte boundary, then an SP alignment fault exception is generated. For more information, see <span class="xref">'SP alignment checking'</span>.</p>
    
      <p>If <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE == <span class="binarynumber">0b0</span>, the field is IGNORED for all purposes other than direct reads and writes of the register.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-4_4-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES1</span>.</p>
    </div><h4 id="fieldset_0-3_3">SA, bit [3]</h4><div class="field">
      <p>SP Alignment check enable. When set to 1, if a load or store instruction executed at EL2 uses the SP as the base address and the SP is not aligned to a 16-byte boundary, then an SP alignment fault exception is generated. For more information, see <span class="xref">'SP alignment checking'</span>.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-2_2">C, bit [2]</h4><div class="field">
      <p>Data access Cacheability control, for accesses at EL2 and, when EL2 is enabled in the current Security state and <a href="AArch64-hcr_el2.html">HCR_EL2</a>.{E2H, TGE} == {1, 1}, EL0</p>
    <table class="valuetable"><tr><th>C</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td><p>The following are Non-cacheable for all levels of data and unified cache:</p>
<ul>
<li>
<p>Data accesses to Normal memory from EL2.</p>

</li><li>
<p>When <a href="AArch64-hcr_el2.html">HCR_EL2</a>.{E2H, TGE} != {1, 1}, Normal memory accesses to the EL2 translation tables.</p>

</li><li>
<p>When EL2 is enabled in the current Security state and <a href="AArch64-hcr_el2.html">HCR_EL2</a>.{E2H, TGE} == {1, 1}:</p>
<ul>
<li>Data accesses to Normal memory from EL0.
</li><li>Normal memory accesses to the EL2&amp;0 translation tables.
</li></ul>

</li></ul></td></tr><tr><td class="bitfield">0b1</td><td><p>This control has no effect on the Cacheability of:</p>
<ul>
<li>
<p>Data access to Normal memory from EL2.</p>

</li><li>
<p>When <a href="AArch64-hcr_el2.html">HCR_EL2</a>.{E2H, TGE} != {1, 1}, Normal memory accesses to the EL2 translation tables.</p>

</li><li>
<p>When EL2 is enabled in the current Security state and <a href="AArch64-hcr_el2.html">HCR_EL2</a>.{E2H, TGE} == {1, 1}:</p>
<ul>
<li>Data accesses to Normal memory from EL0.
</li><li>Normal memory accesses to the EL2&amp;0 translation tables.
</li></ul>

</li></ul></td></tr></table><p>This bit has no effect on the EL3 translation regime.</p>
<p>When EL2 is disabled in the current Security state or <a href="AArch64-hcr_el2.html">HCR_EL2</a>.{E2H, TGE} != {1, 1}, this bit has no effect on the EL1&amp;0 translation regime.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><h4 id="fieldset_0-1_1">A, bit [1]</h4><div class="field">
      <p>Alignment check enable. This is the enable bit for Alignment fault checking at EL2 and, when EL2 is enabled in the current Security state and <a href="AArch64-hcr_el2.html">HCR_EL2</a>.{E2H, TGE} == {1, 1}, EL0.</p>
    <table class="valuetable"><tr><th>A</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td><p>Alignment fault checking is disabled when executing at EL2.</p>
<p>When EL2 is enabled in the current Security state and <a href="AArch64-hcr_el2.html">HCR_EL2</a>.{E2H, TGE} == {1, 1}, alignment fault checking disabled when executing at EL0.</p>
<p>Alignment checks on some instructions are not disabled by this control. For more information, see <span class="xref">'Alignment of data accesses'</span>.</p></td></tr><tr><td class="bitfield">0b1</td><td><p>Alignment fault checking is enabled when executing at EL2.</p>
<p>When EL2 is enabled in the current Security state and <a href="AArch64-hcr_el2.html">HCR_EL2</a>.{E2H, TGE} == {1, 1}, alignment fault checking enabled when executing at EL0.</p>
<p>All instructions that load or store one or more registers have an alignment check that the address being accessed is aligned to the size of the data element(s) being accessed. If this check fails it causes an Alignment fault, which is taken as a Data Abort exception.</p></td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-0_0">M, bit [0]</h4><div class="field">
      <p>MMU enable for EL2 or EL2&amp;0 stage 1 address translation.</p>
    <table class="valuetable"><tr><th>M</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td><p>When <a href="AArch64-hcr_el2.html">HCR_EL2</a>.{E2H, TGE} != {1, 1}, EL2 stage 1 address translation disabled.</p>
<p>When <a href="AArch64-hcr_el2.html">HCR_EL2</a>.{E2H, TGE} == {1, 1}, EL2&amp;0 stage 1 address translation disabled.</p>
<p>See the SCTLR_EL2.I field for the behavior of instruction accesses to Normal memory.</p></td></tr><tr><td class="bitfield">0b1</td><td><p>When <a href="AArch64-hcr_el2.html">HCR_EL2</a>.{E2H, TGE} != {1, 1}, EL2 stage 1 address translation enabled.</p>
<p>When <a href="AArch64-hcr_el2.html">HCR_EL2</a>.{E2H, TGE} == {1, 1}, EL2&amp;0 stage 1 address translation enabled.</p></td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL2, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><div class="access_mechanisms"><h2>Accessing SCTLR_EL2</h2>
        <p>When <a href="AArch64-hcr_el2.html">HCR_EL2</a>.E2H is 1, without explicit synchronization, access from EL2 using the mnemonic SCTLR_EL2 or SCTLR_EL1 are not guaranteed to be ordered with respect to accesses using the other mnemonic.</p>
      <p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRS &lt;Xt&gt;, SCTLR_EL2</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b11</td><td>0b100</td><td>0b0001</td><td>0b0000</td><td>0b000</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; HCR_EL2.NV == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    X[t, 64] = SCTLR_EL2;
elsif PSTATE.EL == EL3 then
    X[t, 64] = SCTLR_EL2;
                </p><h4 class="assembler">MSR SCTLR_EL2, &lt;Xt&gt;</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b11</td><td>0b100</td><td>0b0001</td><td>0b0000</td><td>0b000</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; HCR_EL2.NV == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    SCTLR_EL2 = X[t, 64];
elsif PSTATE.EL == EL3 then
    SCTLR_EL2 = X[t, 64];
                </p><h4 class="assembler"><span class="condition">
When FEAT_VHE is implemented
            </span><br/>MRS &lt;Xt&gt;, SCTLR_EL1</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b11</td><td>0b000</td><td>0b0001</td><td>0b0000</td><td>0b000</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; HCR_EL2.TRVM == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_FGT) &amp;&amp; (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') &amp;&amp; HFGRTR_EL2.SCTLR_EL1 == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; HCR_EL2.&lt;NV2,NV1,NV&gt; == '111' then
        X[t, 64] = NVMem[0x110];
    else
        X[t, 64] = SCTLR_EL1;
elsif PSTATE.EL == EL2 then
    if HCR_EL2.E2H == '1' then
        X[t, 64] = SCTLR_EL2;
    else
        X[t, 64] = SCTLR_EL1;
elsif PSTATE.EL == EL3 then
    X[t, 64] = SCTLR_EL1;
                </p><h4 class="assembler"><span class="condition">
When FEAT_VHE is implemented
            </span><br/>MSR SCTLR_EL1, &lt;Xt&gt;</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b11</td><td>0b000</td><td>0b0001</td><td>0b0000</td><td>0b000</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; HCR_EL2.TVM == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_FGT) &amp;&amp; (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') &amp;&amp; HFGWTR_EL2.SCTLR_EL1 == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; HCR_EL2.&lt;NV2,NV1,NV&gt; == '111' then
        NVMem[0x110] = X[t, 64];
    else
        SCTLR_EL1 = X[t, 64];
elsif PSTATE.EL == EL2 then
    if HCR_EL2.E2H == '1' then
        SCTLR_EL2 = X[t, 64];
    else
        SCTLR_EL1 = X[t, 64];
elsif PSTATE.EL == EL3 then
    SCTLR_EL1 = X[t, 64];
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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